Tetsuya Iida

According to our database, Tetsuya Iida authored at least 11 papers between 1994 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC.

Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito

IEEE J. Solid State Circuits, 2012

A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs.

Toshihisa Watabe, Kazuya Kitamura, Takehide Sawamoto, Tomohiko Kosugi, Tomoyuki Akahori, Tetsuya Iida, Keigo Isobe, Takashi Watanabe, Hiroshi Shimamoto, Hiroshi Ohtake, Satoshi Aoyama, Shoji Kawahito, Norifumi Egami

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

Strategic multi-store opening under financial constraint.

Tetsuya Iida, Nobuo Matsubayashi

Eur. J. Oper. Res., 2011

An 80μVrms-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC.

Min-Woong Seo, Sungho Suh, Tetsuya Iida, Hiroshi Watanabe, Taishi Takasawa, Tomoyuki Akahori, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Shoji Kawahito

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2007

Special Section on Analog Circuits and Related SoC Integration Technologies.

Tetsuya Iida

IEICE Trans. Electron., 2007

2005

A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS.

Hirotomo Ishii, Ken Tanabe, Tetsuya Iida

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2000

A straightforward design of mismatch-shaped multi-bit ΔΣ D/A systems.

Zdzislaw Czarnul, K. Oda, Tetsuya Iida

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998

A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching.

Akira Yasuda, Hiroshi Tanimoto, Tetsuya Iida

IEEE J. Solid State Circuits, 1998

1997

A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit.

Yasuhiro Sugimoto, Tetsuya Iida

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier.

Tetsuro Itakura, Tetsuya Iida

IEEE J. Solid State Circuits, 1996

1994

Principles of nonlinearity Cancellation in Linear MOS Systems using MRC Circuits.

Zdzislaw Czarnul, Shigetaka Takagi, Nobuo Fujii, Tetsuya Iida, Takeshi Yanagisawa

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994