Tetsuro Nakamura

According to our database, Tetsuro Nakamura authored at least 7 papers between 1992 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Spatial- and time- division multiplexing in CNN accelerator.

Tetsuro Nakamura, Shogo Saito, Kei Fujimoto, Masashi Kaneko, Akinori Shiraga

Parallel Comput., 2022

2021

Time-Division Multiplexing for FPGA Considering CNN Model Switch Time.

Tetsuro Nakamura, Shogo Saito, Kei Fujimoto, Masashi Kaneko, Akinori Shiraga

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

1994

High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.

Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

IEEE Trans. Computers, 1994

A CMOS integrated circuit for multichannel multiple-subject biotelemetry using bidirectional optical transmissions [weightlessness in space effects application].

Shoji Kawahito, Susumu Ueda, Maloto Ishida, Tetsuro Nakamura, Shiro Usui, Shunji Nagaoka

IEEE Trans. Biomed. Eng., 1994

1993

Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations.

Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1993

1992

Implementation and design of biosignal optical telemetry system based on enforced synchronization.

Nobuo Karita, Shoji Kawahito, Makoto Ishida, Shiro Usui, Tetsuro Nakamura, Masafumi Nishikado, Shunji Nagaoka

Syst. Comput. Jpn., 1992

Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI.

Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992