Tetsuro Itakura

According to our database, Tetsuro Itakura authored at least 64 papers between 1995 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.

Toshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2019

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits.

Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura

IEEE Trans. Very Large Scale Integr. Syst., 2019

2017

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.

Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.

Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura

IEEE J. Solid State Circuits, 2016

A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing.

Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA.

Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC.

Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.

Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB.

Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting.

Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS.

Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors.

Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.

Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC.

Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal.

Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS.

Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier.

Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS.

Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

All-digital background calibration for time-interleaved ADC using pseudo aliasing signal.

Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Harmonic Signal Rejection Schemes of Polyphase Downconverters.

Takafumi Yamaji, Hiroshi Tanimoto, Junya Matsuno, Tetsuro Itakura

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch.

Ippei Akita, Tetsuro Itakura, Kei Shiraishi

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique.

Masanori Furuta, Mai Nozawa, Tetsuro Itakura

IEEE J. Solid State Circuits, 2011

A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop.

Akihide Sai, Takafumi Yamaji, Tetsuro Itakura

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller.

Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS.

Ippei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata

Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier.

Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System.

Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Phase Compensation Techniques for Low-Power Operational Amplifiers.

Rui Ito, Tetsuro Itakura

IEICE Trans. Electron., 2010

A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers.

Tomohiko Ito, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Foreword.

Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A 0.06mm² 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS.

Masanori Furuta, Mai Nozawa, Tetsuro Itakura

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter.

Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters.

Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals.

Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers.

Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura

IEICE Trans. Electron., 2008

An area-efficient sampling rate converter using negative feedback technique.

Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme.

Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura

IEEE J. Solid State Circuits, 2007

A Fast <i>f_c</i> Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems.

Osamu Watanabe, Rui Ito, Shigehito Saigusa, Tadashi Arai, Tetsuro Itakura

IEICE Trans. Electron., 2007

A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS.

Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller.

Hidenori Okuni, Rui Ito, Hiroshi Yoshida, Tetsuro Itakura

Proceedings of the IEEE 18th International Symposium on Personal, 2007

A novel quality factor tuning scheme for active-RC filters.

Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers.

Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura

IEEE J. Solid State Circuits, 2006

Low-Power Design of 10-bit 80-MSPS Pipeline ADCs.

Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Balanced 3-phase analog signal processing for radio communications.

Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA.

Hiroshi Yoshida, Takehiko Toyoda, Makoto Arai, Ryuichi Fujimoto, Toshiya Mitomo, Masato Ishii, Rui Ito, Tadashi Arai, Tetsuro Itakura, Hiroshi Tsurumi

IEICE Trans. Electron., 2005

A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA.

Takeshi Ueno, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Phase Compensation Technique for a Low-Power Transconductor.

Rui Ito, Tetsuro Itakura, Tadashi Arai

IEICE Trans. Electron., 2005

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter.

Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura

IEICE Electron. Express, 2005

A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS.

Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

A +10-dBm IIP₃ SiGe mixer with IM₃ cancellation technique.

Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura

IEEE J. Solid State Circuits, 2004

Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design.

Tomohiko Ito, Takafumi Yamaji, Daisuke Kurose, Tetsuro Itakura

IEICE Electron. Express, 2004

2003

A four-input beam-forming downconverter for adaptive antennas.

Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi, Tetsuro Itakura

IEEE J. Solid State Circuits, 2003

A 402-output TFT-LCD driver IC with power control based on the number of colors selected.

Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda

IEEE J. Solid State Circuits, 2003

A 1-V 2-GHz CMOS Up-Converter Using Self-Switching Mixers.

Toshiyuki Umeda, Shoji Otaka, Kenji Kojima, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range.

Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura

IEEE J. Solid State Circuits, 2002

A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching.

Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura

IEEE J. Solid State Circuits, 2002

A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer.

Osamu Watanabe, Takafumi Yamaji, Tetsuro Itakura, Ichiro Hattori

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC.

Tetsuro Itakura, Hironori Minamizaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors.

Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1999

A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC.

Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu

IEEE J. Solid State Circuits, 1999

A 2 V_pp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF.

Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Tadashi Arai

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1996

An offset-free LPF for π/4-shift QPSK signal generator.

Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda

IEEE J. Solid State Circuits, 1996

A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier.

Tetsuro Itakura, Tetsuya Iida

IEEE J. Solid State Circuits, 1996

1995

Principle and applications of an autocharge-compensated sample and hold circuit.

Takeshi Shima, Tetsuro Itakura, Shigeru Yamada, Hironori Minamizaki, Takeshi Ishioka

IEEE J. Solid State Circuits, August, 1995