Tetsuo Tada

According to our database, Tetsuo Tada authored at least 4 papers between 1996 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2004

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.

Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Opportunities with the open architecture test system.

Tetsuo Tada

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2001

Test cost reduction by at-speed BISR for embedded DRAMs.

Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1996

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.

Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996