Tetsuo Matsui
Orcid: 0000-0002-5567-3902
According to our database1,
Tetsuo Matsui
authored at least 8 papers
between 2005 and 2023.
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Bibliography
2023
A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2021
A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction.
IEEE J. Solid State Circuits, 2021
2020
9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Gauge Neural Network with Z(2) Synaptic Variables: Phase Structure and Simulation of Learning and Recalling Patterns.
Neural Process. Lett., 2018
2016
Neural Network for Quantum Brain Dynamics: 4D CP ^1 1 +U(1) Gauge Theory on Lattice and Its Phase Structure.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
2005
Proceedings of the IEEE International Joint Conference on Neural Networks, 2005