Tetsu Nagamatsu

According to our database1, Tetsu Nagamatsu authored at least 3 papers between 1992 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1992
1993
1994
1995
1996
0
1
2
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1996
A 0.9-V, 150-MHz, 10-mW, 4 mm<sup>2</sup>, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.
IEEE J. Solid State Circuits, 1996

1994
A 200 MHz 13 mm<sup>2</sup> 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme.
IEEE J. Solid State Circuits, December, 1994

1992
0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file.
IEEE J. Solid State Circuits, November, 1992


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