Teruo Tanimoto

According to our database, Teruo Tanimoto authored at least 26 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms.

Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

CoRR, 2024

SFQ counter-based precomputation for large-scale cryogenic VQE machines.

Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

CoRR, 2024

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines.

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

IEEE Comput. Archit. Lett., 2024

2023

Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers.

KuanYi Ng, Aalaa M. A. Babai, Teruo Tanimoto, Satoshi Kawakami, Koji Inoue

J. Inf. Process., 2023

Circuit designs for practical-scale fault-tolerant quantum computing.

Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code.

Wang Liao, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno, Yuuki Tokunaga

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

An Edge Autonomous Lamp Control with Camera Feedback.

Satoshi Matsushita, Teruo Tanimoto, Satoshi Kawakami, Takatsugu Ono, Koji Inoue

Proceedings of the 8th IEEE World Forum on Internet of Things, 2022

Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays.

Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, Teruo Tanimoto

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device.

Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, Koji Inoue

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

XQsim: modeling cross-technology control processors for 10+K qubit quantum computers.

Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, Jangwoo Kim

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021

Superconductor Computing for Neural Networks.

Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue

IEEE Micro, 2021

2020

32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic.

Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices.

Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Practical Error Modeling Toward Realistic NISQ Simulation.

Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

How Many Trials Do We Need for Reliable NISQ Computing?

Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Enhancing a manycore-oriented compressed cache for GPGPU.

Keitaro Oka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Koji Inoue

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

2019

Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

2017

Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue

J. Inf. Process., 2017

Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki

IEEE Comput. Archit. Lett., 2017

Heavy Tails in Program Structure.

Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan

IEEE Comput. Archit. Lett., 2017

Why do programs have heavy tails?

Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

2015

A Flexible Direct Attached Storage for a Data Intensive Application.

Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, Jun Tanaka

IEICE Trans. Inf. Syst., 2015

2014

Hardware-assisted scalable flow control of shared receive queue.

Teruo Tanimoto, Takatsugu Ono, Kohta Nakashima, Takashi Miyoshi

Proceedings of the 2014 International Conference on Supercomputing, 2014

FlexDAS: A flexible direct attached storage for I/O intensive applications.

Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, Jun Tanaka

Proceedings of the 2014 IEEE International Conference on Big Data (IEEE BigData 2014), 2014

2012

Scalability-based manycore partitioning.

Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012