Teruo Tanaka

According to our database, Teruo Tanaka authored at least 23 papers between 1992 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Light Weight Coarse Grid Aggregation for Smoothed Aggregation Algebraic Multigrid Solver.

Akihiro Fujii, Teruo Tanaka, Kengo Nakajima

IEEE Access, 2024

2023

Parallelization of Automatic Tuning for Hyperparameter Optimization of Pedestrian Route Prediction Applications using Machine Learning.

Sorataro Fujika, Yuga Yajima, Teruo Tanaka, Akihiro Fujii, Yuka Kato, Satoshi Ohshima, Takahiro Katagiri

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2023

2019

Time Segment Correction Method for Parallel Time Integration.

Akihiro Fujii, Shigeo Kaneko, Teruo Tanaka, Takeshi Iwashita

J. Inf. Process., 2019

Acceleration of Symmetric Sparse Matrix-Vector Product using Improved Hierarchical Diagonal Blocking Format.

Ryo Muro, Akihiro Fujii, Teruo Tanaka

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2019

2018

Algebraic Multigrid Solver Using Coarse Grid Aggregation with Independent Aggregation.

Naoya Nomura, Akihiro Fujii, Teruo Tanaka, Osni Marques, Kengo Nakajima

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017

D-Spline Performance Tuning Method Flexibly Responsive to Execution Time Perturbation.

Guning Fan, Masayoshi Mochizuki, Akihiro Fujii, Teruo Tanaka, Takahiro Katagiri

Proceedings of the Parallel Processing and Applied Mathematics, 2017

Fast Multidimensional Performance Parameter Estimation with Multiple One-Dimensional d-Spline Parameter Search.

Masayoshi Mochizuki, Akihiro Fujii, Teruo Tanaka

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016

Performance Analysis of SA-AMG Method by Setting Extracted Near-Kernel Vectors.

Naoya Nomura, Akihiro Fujii, Teruo Tanaka, Kengo Nakajima, Osni Marques

Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016

SIMD Parallel Sparse Matrix-Vector and Transposed-Matrix-Vector Multiplication in DD Precision.

Toshiaki Hishinuma, Hidehiko Hasegawa, Teruo Tanaka

Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016

Xev-GMP: Automatic Code Generation for GMP Multiple-Precision Code from C Code.

Toshiaki Hishinuma, Takuma Sakakibara, Akihiro Fujii, Teruo Tanaka, Shoichi Hirasawa

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015

Performance Analysis of the Chebyshev Basis Conjugate Gradient Method on the K Computer.

Yosuke Kumagai, Akihiro Fujii, Teruo Tanaka, Yusuke Hirota, Takeshi Fukaya, Toshiyuki Imamura, Reiji Suda

Proceedings of the Parallel Processing and Applied Mathematics, 2015

Enhancement of Incremental Performance Parameter Estimation on ppOpen-AT.

Riku Murata, Jun Irie, Akihiro Fujii, Teruo Tanaka, Takahiro Katagiri

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

2014

Implementation of d-Spline-based incremental performance parameter estimation method with ppOpen-AT.

Teruo Tanaka, Ryo Otsuka, Akihiro Fujii, Takahiro Katagiri, Toshiyuki Imamura

Sci. Program., 2014

Mixed-Precision AMG method for Many Core Accelerators.

Yuki Sumiyoshi, Akihiro Fujii, Akira Nukada, Teruo Tanaka

Proceedings of the 21st European MPI Users' Group Meeting, 2014

2013

AVX Acceleration of DD Arithmetic Between a Sparse Matrix and Vector.

Toshiaki Hishinuma, Akihiro Fujii, Teruo Tanaka, Hidehiko Hasegawa

Proceedings of the Parallel Processing and Applied Mathematics, 2013

2006

<i>d-Spline</i> Based Incremental Parameter Estimation in Automatic Performance Tuning.

Teruo Tanaka, Takahiro Katagiri, Toshitsugu Yuba

Proceedings of the Applied Parallel Computing. State of the Art in Scientific Computing, 2006

1998

Dynamic Gateways: A Novel Approach to Improve Networking Performance and Availability on Parallel Servers.

Frederico B. Maciel, Nobutoshi Sagawa, Teruo Tanaka

Proceedings of the High-Performance Computing and Networking, 1998

1997

Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201.

Yoshiko Yasuda, Hiroaki Fujii, Hideya Akashi, Yasuhiro Inagami, Teruo Tanaka, Junji Nakagoshi, Hideo Wada, Tsutomu Sumimoto

Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1994

An interprocessor memory access arbitrating scheme for the S-3800 vector supercomputer.

Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Yazawa, Teruo Tanaka, Yoshiko Tamaki, Yasuhiro Inagami

Proceedings of the International Symposium on Parallel Architectures, 1994

Distributed storage control unit for the Hitachi S-3800 multivector supercomputer.

Katsuyoshi Kitai, Tadaaki Isobe, Tadayuki Sakakibara, Shigeko Yazawa, Yoshiko Tamaki, Teruo Tanaka, Kouichi Ishii

Proceedings of the 8th international conference on Supercomputing, 1994

1993

Scalable Parallel Memory Architecture with a Skew Scheme.

Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Yazawa, Teruo Tanaka, Yasuhiro Inagami, Yoshiko Tamaki

Proceedings of the 7th international conference on Supercomputing, 1993

Parallel Processing Architecture for the Hitachi S-3800 Shared-Memory Vector Multiprocessor.

Katsuyoshi Kitai, Tadaaki Isobe, Yoshikazu Tanaka, Yoshiko Tamaki, Masakazu Fukagawa, Teruo Tanaka, Yasuhiro Inagami

Proceedings of the 7th international conference on Supercomputing, 1993

1992

Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors.

Naoki Hamanaka, Junji Nakagoshi, Teruo Tanaka

Proceedings of the Parallel Processing: CONPAR 92, 1992