Terumine Hayashi

According to our database, Terumine Hayashi authored at least 28 papers between 1986 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Obstacle to training SpikeProp networks - Cause of surges in training process -.

Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi

Proceedings of the International Joint Conference on Neural Networks, 2009

2008

Shape of error surfaces in SpikeProp.

Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi

Proceedings of the International Joint Conference on Neural Networks, 2008

2007

Enhancing both generalization and fault tolerance of multilayer neural networks.

Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi

Proceedings of the International Joint Conference on Neural Networks, 2007

Descriptive Answer Clustering System for Immediate Feedback.

Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita

Proceedings of the Supporting Learning Flow through Integrative Technologies, 2007

2006

Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities.

Haruhiko Takase, Hidehiko Kita, Terumine Hayashi

Proceedings of the International Joint Conference on Neural Networks, 2006

Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing.

Terumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita

Proceedings of the 15th Asian Test Symposium, 2006

2005

On Test Data Compression Using Selective Don't-Care Identification.

Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase

J. Comput. Sci. Technol., 2005

A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture.

Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Test data compression technique using selective don't-care identification.

Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Manipulation of hidden units activities for fault tolerant multi-layer neural networks.

Yusei Katsuda, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi

Proceedings of the IEEE International Symposium on Computational Intelligence in Robotics and Automation: Computational Intelligence in Robotics and Automation for the New Millennium, 2003

Between-Core Vector Overlapping for Test Cost Reduction in Core Testing.

Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2001

An enhanced fault model for high defect coverage.

Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi

Syst. Comput. Jpn., 2001

Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems.

Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Evaluation Function for Fault Tolerant Multi-Layer Neural Networks.

Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

Cyclic greedy generation method for limited number of IDDQ tests.

Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits.

Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki

Syst. Comput. Jpn., 1999

A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.

Tsuyoshi Shinogi, Terumine Hayashi

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition.

Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault.

Tsuyoshi Shinogi, Terumine Hayashi

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On a Logical Fault Model H1SGLF for Enhancing Defect Coverage.

Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.

Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits.

Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1993

Sequential circuit test generation by real number simulation.

Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi

Syst. Comput. Jpn., 1993

1992

Sequential Test Generation Based on Real-Value Logic.

Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Timing-Oriented Routers for PCB Layout Design of High-Performance Computers.

Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

LSI module placement methods using neural computation networks.

Hiroshi Date, Mitsuho Seki, Terumine Hayashi

Proceedings of the IJCNN 1990, 1990

1989

Enhanced Delay Test Generator for High-Speed Logic LSIs.

Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama

Proceedings of the Proceedings International Test Conference 1989, 1989

1986

A delay test system for high speed logic LSI's.

Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986