Teruki Someya
Orcid: 0000-0002-8506-1384
According to our database1,
Teruki Someya
authored at least 20 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
A BJT-Based Temperature Sensor with $\pm 0.1^{\circ}\mathrm{C}(3\sigma)$ Inaccuracy from -55°C to 125°C and a 0.85pJ.K<sup>2</sup> Resolution FoM Using Continuous-Time Readout.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal.
IEEE J. Solid State Circuits, 2022
A 0.37mm<sup>2</sup> Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components.
IEICE Trans. Electron., 2022
A 210nW BJT-based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -15°C to 85°C.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications.
IEICE Trans. Electron., 2020
2019
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage.
IEEE J. Solid State Circuits, 2019
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Trans. Electron., 2017
2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015
2013
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2006
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006