Teruhisa Shimizu

According to our database, Teruhisa Shimizu authored at least 4 papers between 1994 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR.

Shoji Yoshida, Shigeya Tanaka, Kotaro Matsuo, Takashi Hotta, Hideo Sawamoto, Teruhisa Shimizu

Syst. Comput. Jpn., 1998

1996

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.

Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

IEEE J. Solid State Circuits, 1996

1995

A superscalar RISC processor with pseudo vector processing feature.

Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

A 120-MHz BiCMOS superscalar RISC processor.

Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura

IEEE J. Solid State Circuits, April, 1994