Teruhiko Amano

According to our database, Teruhiko Amano authored at least 7 papers between 2000 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM.

Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.

Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai

IEEE J. Solid State Circuits, 2013

2005

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.

Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

2003

A Low Power Embedded DRAM Macro for Battery-Operated LSIs.

Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2001

Design methodology of embedded DRAM with virtual-socket architecture.

Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2001

2000

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

Design methodology of the embedded DRAM with the virtual socket architecture.

Mitsuya Kinoshita, Tadaaki Yamauchi, Teruhiko Amano, Katsumi Dosaka, Kenshin Arimoto

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000