Teru Yoneyama

According to our database, Teru Yoneyama authored at least 9 papers between 1998 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2003

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values.

Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally.

Tsutomu Suzuki, Takao Oura, Teru Yoneyama, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values.

Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values.

Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A low voltage floating resistor having positive and negative resistance values.

Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Two floating resistor circuits and their applications to synaptic weights in analog neural networks.

Shashidhar Tantry, Teru Yoneyama, Hideki Asai

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Design Method of Limit Cycle Generator by Hysteresis Neural Networks.

Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999

Design method of neural networks for limit cycle generator.

Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai

Proceedings of the International Joint Conference Neural Networks, 1999

1998

Neural network simulator for spatiotemporal pattern analysis.

Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998