Terry I. Chappell

According to our database, Terry I. Chappell authored at least 6 papers between 1988 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2001

A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit.

Glenn Hinton, Michael Upton, David J. Sager, Darrell Boggs, Douglas M. Carmean, Patrice Roussel, Terry I. Chappell, Thomas D. Fletcher, Mark S. Milshtein, Milo Sprague, Samie Samaan, Robert Murray

IEEE J. Solid State Circuits, 2001

1995

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.

Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, Jack Y.-C. Sun, Michael R. Polcari, Bijan Davari

IBM J. Res. Dev., 1995

1992

On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM.

Stanley E. Schuster, Terry I. Chappell, Barbara A. Chappell, Robert L. Franch

IEEE J. Solid State Circuits, July, 1992

1991

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture.

Terry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, James W. Allan, Stephen P. Klepner, Rajiv V. Joshi, Robert L. Franch

IEEE J. Solid State Circuits, November, 1991

1989

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces.

Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle

IEEE J. Solid State Circuits, August, 1989

1988

Fast CMOS ECL receivers with 100-mV worst-case sensitivity.

Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle

IEEE J. Solid State Circuits, February, 1988