Terry I. Chappell

According to our database1, Terry I. Chappell authored at least 5 papers between 1988 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1988
1990
1992
1994
1996
1998
2000
0
1
2
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2001
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit.
IEEE J. Solid State Circuits, 2001

1995
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM J. Res. Dev., 1995

1992
On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM.
IEEE J. Solid State Circuits, July, 1992

1989
A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces.
IEEE J. Solid State Circuits, August, 1989

1988
Fast CMOS ECL receivers with 100-mV worst-case sensitivity.
IEEE J. Solid State Circuits, February, 1988


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