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Teppei Yamazaki

According to our database1, Teppei Yamazaki authored at least 5 papers between 2010 and 2017.

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Bibliography

2017
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl.
[BibTeX]
[DOI]
Nuray At
,
Jean-Luc Beuchat
,
Eiji Okamoto
,
Ismail San
,
Teppei Yamazaki
J. Parallel Distributed Comput., 2017

2014
Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA.
[BibTeX]
[DOI]
Nuray At
,
Jean-Luc Beuchat
,
Eiji Okamoto
,
Ismail San
,
Teppei Yamazaki
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2011
A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO.
[BibTeX]
[DOI]
Jean-Luc Beuchat
,
Eiji Okamoto
,
Teppei Yamazaki
J. Cryptogr. Eng., 2011

2010
A Compact FPGA Implementation of the SHA-3 Candidate ECHO.
[BibTeX]
[DOI]
Jean-Luc Beuchat
,
Eiji Okamoto
,
Teppei Yamazaki
IACR Cryptol. ePrint Arch., 2010

Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA.
[BibTeX]
[DOI]
Jean-Luc Beuchat
,
Eiji Okamoto
,
Teppei Yamazaki
IACR Cryptol. ePrint Arch., 2010


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