Telajala Venkata Mahendra
Orcid: 0000-0003-4477-3956
According to our database1,
Telajala Venkata Mahendra
authored at least 14 papers
between 2016 and 2024.
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Bibliography
2024
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine.
Integr., 2024
2023
2021
IET Circuits Devices Syst., 2021
2020
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
J. Inf. Sci. Eng., 2020
Low-power content addressable memory design using two-layer P-N match-line control and sensing.
Integr., 2020
IET Comput. Digit. Tech., 2020
2019
Low discharge precharge free matchline structure for energy-efficient search using CAM.
Integr., 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
2018
Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory.
IEEE Trans. Consumer Electron., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Proceedings of the 2016 International Conference on Information Technology, 2016