Tejinder Singh Sandhu
Orcid: 0000-0002-3615-3717
According to our database1,
Tejinder Singh Sandhu
authored at least 5 papers
between 2010 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2023
A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
2019
Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
Beyond Rail-to-Rail Compliant Current Sources for Mismatch-Insensitive Voltage-to-Time Conversion.
IEEE Trans. Very Large Scale Integr. Syst., 2018
2016
A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2010
A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2010