Te-Hui Chen

According to our database, Te-Hui Chen authored at least 7 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

High-speed, low cost test platform using FPGA technology.

Te-Hui Chen

PhD thesis, 2017

2016

Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus.

Nicholas Tzou, Debesh Bhatta, Xian Wang, Te-Hui Chen, Sen-Wen Hsiao, Barry J. Muldrey, Hyun Woo Choi, Abhijit Chatterjee

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 40Gbps economic extension board and FPGA-based testing platform.

Te-Hui Chen, David C. Keezer

Proceedings of the 21th IEEE European Test Symposium, 2016

An Ultra-High-Speed Test Module and FPGA-Based Development Platform.

Te-Hui Chen, David C. Keezer

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

An FPGA-based ATE extension module for low-cost multi-GHz memory test.

David C. Keezer, Te-Hui Chen, Thomas Moon, D. T. Stonecypher, Abhijit Chatterjee, Hyun Woo Choi, Sungyeol Kim, Hosun Yoo

Proceedings of the 20th IEEE European Test Symposium, 2015

2013

Practical methods for extending ATE to 40 and 50Gbps.

David C. Keezer, Carl Edward Gray, Te-Hui Chen, Ashraf Majid

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter.

David C. Keezer, Te-Hui Chen, Carl Edward Gray, Hyun Woo Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo

Proceedings of the 2012 IEEE International Test Conference, 2012