Tatsuyuki Ishikawa

According to our database, Tatsuyuki Ishikawa authored at least 5 papers between 2005 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule.

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A parallel LSI architecture for LDPC decoder improving message-passing schedule.

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-throughput decoder for low-density parity-check code.

Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm.

Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005