Tatsuya Saito
Orcid: 0000-0001-8527-9108
According to our database1,
Tatsuya Saito
authored at least 22 papers
between 2004 and 2024.
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Bibliography
2024
Understated Haptics: Physicalization of Tactile Memories through a Co-creative Practice between Human and Nonhuman.
Proceedings of the SIGGRAPH Asia 2024 Art Papers, 2024
2023
A Proposal of an Axial-Flux Permanent-Magnet Machine Employing SMC Core With Tooth-Tips Constructed by One-Pressing Process: Improving Torque and Manufacturability.
IEEE Access, 2023
Proceedings of the SIGGRAPH Asia 2023 Posters, 2023
Proceedings of the SIGGRAPH Asia 2023 XR, 2023
Proceedings of the 23rd International Conference on New Interfaces for Musical Expression, 2023
Proceedings of the Augmented Humans International Conference 2023, 2023
2018
A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory.
Proceedings of the International SoC Design Conference, 2018
2013
Study on supporting technology for operational procedure design of IT systems in cloud-era datacenters.
Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013
Proceedings of the Knowledge and Systems Engineering, 2013
A procedure for n-D Fornasini-Marchesini state-space model realization based on right matrix fraction description.
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Multidimens. Syst. Signal Process., 2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.
IEEE J. Solid State Circuits, 2009
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1<sup>st</sup>-order ΔΣ modulator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the Human-Computer Interaction. Novel Interaction Methods and Techniques, 2009
2008
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2004
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking.
IEEE J. Solid State Circuits, 2004