Tatsuya Hirose

According to our database, Tatsuya Hirose authored at least 12 papers between 2002 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Abstraction Multimodal Low-Dimensional Representation from High-Dimensional Posture Information and Visual Images.

Tatsuya Hirose, Tadahiro Taniguchi

J. Robotics Mechatronics, 2013

NTMobile: new end-to-end communication architecture in IPv4 and IPv6 networks.

Hidekazu Suzuki, Katsuhiro Naito, Kazuma Kamienoo, Tatsuya Hirose, Akira Watanabe

Proceedings of the 19th Annual International Conference on Mobile Computing and Networking, 2013

2012

A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors.

Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2010

A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors.

Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Advanced MMIC Receiver for 94-GHz Band Passive Millimeter-Wave Imager.

Masaru Sato, Tatsuya Hirose, Koji Mizuno

IEICE Trans. Electron., 2009

A 77GHz transceiver in 90nm CMOS.

Yoichi Kawano, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

60 and 77GHz Power Amplifiers in Standard 90nm CMOS.

Toshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology.

Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose

IEEE J. Solid State Circuits, 2007

2005

A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique.

Yusuke Inoue, Masaru Sato, Toshihiro Ohki, Kozo Makiyama, Tsuyoshi Takahashi, Hisao Shigematsu, Tatsuya Hirose

IEEE J. Solid State Circuits, 2005

2004

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology.

Toshihide Suzuki, Tsuyoshi Takahashi, Tatsuya Hirose, Masahiko Takikawa

IEEE J. Solid State Circuits, 2004

2002

A 54-GHz distributed amplifier with 6-V_PP output for a 40-Gb/s LiNbO₃ modulator driver.

Hisao Shigematsu, Masaru Sato, Tatsuya Hirose, Yuu Watanabe

IEEE J. Solid State Circuits, 2002

A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology.

Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe

IEEE J. Solid State Circuits, 2002