Tatsuo Higuchi
Affiliations:- Tohoku University
According to our database1,
Tatsuo Higuchi
authored at least 140 papers
between 1977 and 2010.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1992, "For contributions to the theory of multidimensional signal processing and the development of the beyond-binary VLSI signal processing techniques.".
Timeline
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Bibliography
2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
2009
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
J. Multiple Valued Log. Soft Comput., 2009
Int. J. Nanotechnol. Mol. Comput., 2009
2008
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams.
IEEE Trans. Computers, 2008
Int. J. Unconv. Comput., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
J. Multiple Valued Log. Soft Comput., 2007
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.
J. Multiple Valued Log. Soft Comput., 2007
Synthesis of current mirrors based on evolutionary graph generation with transmigration capability.
IEICE Electron. Express, 2007
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
2006
A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic.
IEICE Trans. Electron., 2006
Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the International Conference on Image Processing, 2006
Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller.
Proceedings of the Advances in Biometrics, International Conference, 2006
A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching.
Proceedings of the Advances in Biometrics, International Conference, 2006
2005
J. Multiple Valued Log. Soft Comput., 2005
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects.
J. Multiple Valued Log. Soft Comput., 2005
A compact cluster computer with embedded CPUs and its application to rapid prototyping of fingerprint verification system.
IEICE Electron. Express, 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints.
Proceedings of the 2005 International Conference on Image Processing, 2005
2004
Proceedings of the Parallel Problem Solving from Nature, 2004
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
A systematic approach for analyzing fast addition algorithms using counter tree diagrams.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004
2003
J. Multiple Valued Log. Soft Comput., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Design of a digital reaction-diffusion system for restoring blurred fingerprint images.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A framework of evolutionary graph generation system and its application to circuit synthesis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
VLSI circuit design using an object-oriented framework of evolutionary graph generation system.
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
2002
IEEE Trans. Evol. Comput., 2002
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis.
Proceedings of the Parallel Problem Solving from Nature, 2002
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Proceedings of the Seventh International Conference on Control, 2002
Graph-based individual representation for evolutionary synthesis of arithmetic circuits.
Proceedings of the 2002 Congress on Evolutionary Computation, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Evolutionary graph generation system with transmigration capability for arithmetic circuit design.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
1997
Communication network protocol for real-time distributed control and its LSI implementation.
IEEE Trans. Ind. Electron., 1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997
1996
Minimization of nearest neighbor classifiers based on individual evolutionary algorithm.
Pattern Recognit. Lett., 1996
Neurocomputing, 1996
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
GA-based design of multiplierless 2-D state-space digital filters with very small roundoff noise.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
1995
Individual Evolutionary Algorithm and its Application to Learning of Nearest Neighbor Based MLP.
Proceedings of the From Natural to Artificial Neural Computation, 1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Design of 2-D state-space digital filters with powers-of-two coefficients based on a genetic algorithm.
Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995
Proceedings of the Euro-Par '95 Parallel Processing, 1995
An Evolutionary Algorithm for Solving Multi-Individual-Multi-Task Problems.
Proceedings of the 1995 International Workshop on Biologically Inspired Evolutionary Systems, 1995
1994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers, 1994
J. Robotics Mechatronics, 1994
J. Robotics Mechatronics, 1994
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Design of Multiwave Computing Circuits Based on a Modle of Integrated Opto-Electronic Devices.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994
Optimal Design Method of 2-D IIR Digital Filters Based on a Simple Genetic Algorithm.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994
1993
Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations.
Syst. Comput. Jpn., 1993
Design of 2-d Digital filters Based on the Optimal Decomposition of Magnitude Specifications.
J. Circuits Syst. Comput., 1993
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
Realization of lattice-form separable-denominator 2D adaptive filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1992
Design of an ultrahigher-valued biocomputing system based on set-valued logic networks.
Syst. Comput. Jpn., 1992
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1991
Syst. Comput. Jpn., 1991
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1990
Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation.
Syst. Comput. Jpn., 1990
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits.
Syst. Comput. Jpn., 1990
Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model.
Syst. Comput. Jpn., 1990
J. Robotics Mechatronics, 1990
J. Robotics Mechatronics, 1990
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
1989
Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic.
IEEE J. Solid State Circuits, October, 1989
High-density quaternary logic array chip for knowledge information processing systems.
IEEE J. Solid State Circuits, August, 1989
Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation.
Syst. Comput. Jpn., 1989
Proceedings of the 1989 IEEE International Conference on Robotics and Automation, 1989
1988
IEEE J. Solid State Circuits, February, 1988
Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System.
Syst. Comput. Jpn., 1988
Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation.
Syst. Comput. Jpn., 1988
Computer, 1988
1987
Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic.
Syst. Comput. Jpn., 1987
Syst. Comput. Jpn., 1987
1986
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits.
Syst. Comput. Jpn., 1986
A unified design method of state-space digital filters using system balancing concept.
Proceedings of the IEEE International Conference on Acoustics, 1986
Proceedings of the IEEE International Conference on Acoustics, 1986
Synthesis of minimum sensitivity structures in linear systems using controllability and observability measures.
Proceedings of the IEEE International Conference on Acoustics, 1986
1985
A unified approach to the optimal synthesis of fixed-point state-space digital filters.
IEEE Trans. Acoust. Speech Signal Process., 1985
1981
Another discrete Fourier transform computation with small multiplications via the Walsh transform.
Proceedings of the IEEE International Conference on Acoustics, 1981
1980
A sufficient condition for absence of overflow oscillations in arbitrary digital filters based on the element equations.
Proceedings of the IEEE International Conference on Acoustics, 1980
1979
A state-space approach for elimination of limit cycles in digital filters with arbitrary structures.
Proceedings of the IEEE International Conference on Acoustics, 1979
1978
Proceedings of the eighth international symposium on Multiple-valued logic, 1978
1977
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module.
IEEE Trans. Computers, 1977
Static-Hazard-Free <i>T</i>-Gate for Ternary Memory Element and Its Application to Ternary Counters.
IEEE Trans. Computers, 1977