Tatsumi Yamauchi

According to our database, Tatsumi Yamauchi authored at least 5 papers between 1988 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1996

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.

Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

IEEE J. Solid State Circuits, 1996

1995

A 13.3ns double-precision floating-point ALU and multiplier.

Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor.

Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh

IEEE J. Solid State Circuits, March, 1994

1991

A 6-ns 256-kb BiCMOS TTL SRAM.

Takashi Akioka, Atsushi Hiraishi, Tatsumi Yamauchi, Yuji Yokoyama, Shigeru Takahashi, Masahiro Iwamura, Yutaka Kobayashi, Akira Ide, Nobuyuki Gotou, Kazunori Onozawa, Hideaki Uchida

IEEE J. Solid State Circuits, March, 1991

1988

1.3- mu m CMOS/bipolar standard cell library for VLSI computers.

Takashi Hotta, Kouzaburou Kurita, Hideo Maejima, Masahiro Iwamura, Shigeya Tanaka, Tadaaki Bandoh, Tatsumi Yamauchi, Atsuo Hotta

IEEE J. Solid State Circuits, April, 1988