Tatjana R. Nikolic

Orcid: 0000-0003-2649-4478

Affiliations:
  • University of Nis, Serbia


According to our database1, Tatjana R. Nikolic authored at least 18 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Fingerprinting-assisted UWB-based localization technique for complex indoor environments.
Expert Syst. Appl., 2021

2020
Token ring arbitration scheme for on-chip CDMA bus architectures.
Microelectron. J., 2020

2017
Implementation and evaluation of 2D SEC-DED forward error correction scheme in wireless sensor networks.
Microelectron. Reliab., 2017

Precharged Phase Detector with Zero Dead-Zone and Minimal Blind-Zone.
J. Circuits Syst. Comput., 2017

2016
Improving fault-tolerance capability of on-chip binary CDMA bus.
J. Supercomput., 2016

Reliable data transfer Rendezvous protocol in wireless sensor networks using 2D-SEC-DED encoding technique.
Microelectron. Reliab., 2016

2015
Low-power fault-tolerant interconnect method based on LCDMA and duplication.
Microelectron. Reliab., 2015

Concurrent Generation of Pseudo Random Numbers with LFSR of Fibonacci and Galois Type.
Comput. Informatics, 2015

2014
Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation.
J. Circuits Syst. Comput., 2014

2013
Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Programmable jitter generator.
Int. J. Reason. based Intell. Syst., 2012

Fault tolerant pseudorandom number generator.
Proceedings of the 1st Mediterranean Conference on Embedded Computing, 2012

2010
Address generators for linear systolic array.
Microelectron. Reliab., 2010

Wrapper design for a CDMA bus in SOC.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
CDMA bus-based on-chip interconnect infrastructure.
Microelectron. Reliab., 2009

Multi-functional systolic array with reconfigurable micro-power processing elements.
Microelectron. Reliab., 2009

2004
Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits.
Microelectron. Reliab., 2004

Approach to partially self-checking combinational circuits design.
Microelectron. J., 2004


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