Tarun Kumar Gupta

According to our database, Tarun Kumar Gupta authored at least 21 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DeLTran15: A Deep Lightweight Transformer-Based Framework for Multiclass Classification of Disaster Posts on X.

Saima Saleem, Nabeela Hasan, Anuradha Khattar, Priti Rai Jain, Tarun Kumar Gupta, Monica Mehrotra

IEEE Access, 2024

2023

Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs.

Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta

Microelectron. J., April, 2023

BatTS: a hybrid method for optimizing deep feedforward neural network.

Sichen Pan, Tarun Kumar Gupta, Khalid Raza

PeerJ Comput. Sci., 2023

Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems.

Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta

Microelectron. J., 2023

2022

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor.

Yogesh Shrivastava, Tarun Kumar Gupta

J. Circuits Syst. Comput., 2022

2021

Optimization of Artificial Neural Network: A Bat Algorithm-Based Approach.

Tarun Kumar Gupta, Khalid Raza

Proceedings of the Intelligent Systems Design and Applications, 2021

2020

Optimizing Deep Feedforward Neural Network Architecture: A Tabu Search Based Approach.

Tarun Kumar Gupta, Khalid Raza

Neural Process. Lett., 2020

A novel high-density dual threshold GNRFET SRAM design with improved stability.

Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta

Microprocess. Microsystems, 2020

A 1-bit full adder using CNFET based dual chirality high speed domino logic.

Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey

Int. J. Circuit Theory Appl., 2020

2019

Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM.

Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta

Microelectron. J., 2019

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology.

Sandeep Garg, Tarun Kumar Gupta

J. Circuits Syst. Comput., 2019

ONOFIC-based leakage reduction technique for FinFET domino circuits.

Vijay Kumar Magraiya, Tarun Kumar Gupta

Int. J. Circuit Theory Appl., 2019

FDSTDL: Low-power technique for FinFET domino circuits.

Sandeep Garg, Tarun Kumar Gupta

Int. J. Circuit Theory Appl., 2019

Low leakage domino logic circuit for wide fan-in gates using CNTFET.

Sandeep Garg, Tarun Kumar Gupta

IET Circuits Devices Syst., 2019

ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction.

Vijay Kumar Magraiya, Tarun Kumar Gupta

Circuits Syst. Signal Process., 2019

2018

New Leakage Reduction Techniques for FinFET Technology with Its Application.

Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh

J. Circuits Syst. Comput., 2018

Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network.

Amit Kumar Pandey, Pawan Kumar Verma, Rajesh Verma, Tarun Kumar Gupta

Circuits Syst. Signal Process., 2018

Optimizing Deep Neural Network Architecture: A Tabu Search Based Approach.

Tarun Kumar Gupta, Khalid Raza

CoRR, 2018

2015

An Improved Fuzzy Voting Scheme for Fault Tolerant Systems.

Ram Murti Rawat, Tarun Kumar Gupta, Mohammad Sajid, Shiv Prakash, Dinesh Prasad Sahu, Sohan Kumar Yadav, Chanchal Kumar

Int. J. Appl. Evol. Comput., 2015

Comparative Study of Bakhshālī Square Root Method with Newton's Iterative Method.

Nidhi Handa, Tarun Kumar Gupta, S. L. Singh

Proceedings of Fifth International Conference on Soft Computing for Problem Solving, 2015

2013

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits.

Tarun Kumar Gupta, Kavita Khare

Circuits Syst. Signal Process., 2013