Tarun Kumar Gupta
Orcid: 0000-0001-8061-4771
According to our database1,
Tarun Kumar Gupta
authored at least 21 papers
between 2013 and 2024.
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Bibliography
2024
DeLTran15: A Deep Lightweight Transformer-Based Framework for Multiclass Classification of Disaster Posts on X.
IEEE Access, 2024
2023
Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs.
Microelectron. J., April, 2023
PeerJ Comput. Sci., 2023
Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems.
Microelectron. J., 2023
2022
Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor.
J. Circuits Syst. Comput., 2022
2021
Proceedings of the Intelligent Systems Design and Applications, 2021
2020
Optimizing Deep Feedforward Neural Network Architecture: A Tabu Search Based Approach.
Neural Process. Lett., 2020
Microprocess. Microsystems, 2020
Int. J. Circuit Theory Appl., 2020
2019
Microelectron. J., 2019
A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology.
J. Circuits Syst. Comput., 2019
Int. J. Circuit Theory Appl., 2019
Int. J. Circuit Theory Appl., 2019
IET Circuits Devices Syst., 2019
ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction.
Circuits Syst. Signal Process., 2019
2018
J. Circuits Syst. Comput., 2018
Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network.
Circuits Syst. Signal Process., 2018
CoRR, 2018
2015
Int. J. Appl. Evol. Comput., 2015
Proceedings of Fifth International Conference on Soft Computing for Problem Solving, 2015
2013
Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits.
Circuits Syst. Signal Process., 2013