Tara Ghasempouri

Orcid: 0000-0001-8021-9368

According to our database1, Tara Ghasempouri authored at least 31 papers between 2014 and 2024.

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Bibliography

2024
Survey on Architectural Attacks: A Unified Classification and Attack Model.
ACM Comput. Surv., February, 2024

SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans.
CoRR, 2024

Automatic High Functional Coverage Stimuli Generation for Assertion-based Verification.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators.
Proceedings of the IEEE European Test Symposium, 2024

ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ARTmine: Automatic Association Rule Mining with Temporal Behavior for Hardware Verification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
An automated method for mining high-quality assertion sets.
Microprocess. Microsystems, March, 2023

Anomalous File System Activity Detection Through Temporal Association Rule Mining.
Proceedings of the 9th International Conference on Information Systems Security and Privacy, 2023

2022
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Exploring Factors in a Crossroad Dataset Using Cluster-Based Association Rule Mining.
Proceedings of the 13th International Conference on Ambient Systems, 2022

2021
A Methodology for Automated Mining of Compact and Accurate Assertion Sets.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

LiD-CAT: A Lightweight Detector for Cache ATtacks.
Proceedings of the IEEE European Test Symposium, 2020

SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Adjustable self-healing methodology for accelerated functions in heterogeneous systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A Security Verification Template to Assess Cache Architecture Vulnerabilities.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
Understanding multidimensional verification: Where functional meets non-functional.
Microprocess. Microsystems, 2019

Engineering of an Effective Automatic Dynamic Assertion Mining Platform.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

RTL Assertion Mining with Automated RTL-to-TLM Abstraction.
Proceedings of the 2019 Forum for Specification and Design Languages, 2019

2018
Design Understanding: From Logic to Specification<sup>*</sup>.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Towards Multidimensional Verification: Where Functional Meets Non-Functional.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers.
Proceedings of the IEEE International Test Conference in Asia, 2018

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics.
Proceedings of the IEEE International Test Conference in Asia, 2018

From RTL Liveness Assertions to Cost-Effective Hardware Checkers.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2015
Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.
J. Electron. Test., 2015

On the estimation of assertion interestingness.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Automatic extraction of assertions from execution traces of behavioural models.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
On the reuse of RTL assertions in SystemC TLM verification.
Proceedings of the 15th Latin American Test Workshop, 2014


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