Tapani Ahonen

Orcid: 0000-0003-0304-8790

According to our database1, Tapani Ahonen authored at least 33 papers between 2003 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture.
J. Signal Process. Syst., 2017

Integration issues of a run-time configurable memory management unit to a RISC processor on FPGA.
Microprocess. Microsystems, 2017

FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios.
J. Syst. Archit., 2017

2016
HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms.
J. Signal Process. Syst., 2016

Accelerating Computation on an Android Phone with OpenCL Parallelism and Optimizing Workload Distribution between a Phone and a Cloud Service.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015
Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Design of a hybrid multicore platform for high performance reconfigurable computing.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2014
MPSoC based on Transport Triggered Architecture for baseband processing of an LTE receiver.
J. Syst. Archit., 2014

Constraint-driven frequency scaling in a Coarse Grain Reconfigurable Array.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

FPGA implementation of a flexible synchronizer for cognitive radio applications.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
A LLVM based compiler for COFFEE.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

Evaluation of WCDMA receiver baseband processing on a Multi-Processor System-On-Chip.
Proceedings of the 18th International Conference on Digital Signal Processing, 2013

2012
Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems.
J. Signal Process. Syst., 2012

Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Effects of scaling a coarse-grain reconfigurable array on power and energy consumption.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Reconfigurable multi-processor architecture for streaming applications.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC.
J. Signal Process. Syst., 2011

State of the art baseband DSP platforms for Software Defined Radio: A survey.
EURASIP J. Wirel. Commun. Netw., 2011

Application-driven dimensioning of a Coarse-Grain Reconfigurable Array.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2009
Multicore Software-Defined Radio Architecture for GNSS Receiver Signal Processing.
EURASIP J. Embed. Syst., 2009

Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.
Proceedings of the Embedded Computer Systems: Architectures, 2009

2008
Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications.
J. Syst. Archit., 2008

2007
Applying CDMA Technique to Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Integration of a NoC-Based Multimedia Processing Platform.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Issues in the development of a practical NoC: the Proteo concept.
Integr., 2004

Topology optimization for application-specific networks-on-chip.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

A synthesizable RTL design of asynchronous FIFO.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Design reuse and design for reuse, a case study on HDSL2.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003
Block-wise Extraction of Rent's Exponents for an Extensible Processor.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003


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