Tapan J. Chakraborty

According to our database, Tapan J. Chakraborty authored at least 27 papers between 1988 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

Functional Fmax test-time reduction using novel DFTs for circuit initialization.

Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2010

A Common Language Framework for Next-Generation Embedded Testing.

Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook

IEEE Des. Test Comput., 2010

2008

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.

Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A New Language Approach for IJTAG.

Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

FPGA Prototyping of a Scan Based System-On-Chip Design.

Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A practical approach to comprehensive system test & debug using boundary scan based test architecture.

Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren

Proceedings of the 2007 IEEE International Test Conference, 2007

A TMR Scheme for SEU Mitigation in Scan Flip-Flops.

Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2005

Efficient Test Architecture based on Boundary Scan for Comprehensive System Test.

Tapan J. Chakraborty

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2002

A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.

Tapan J. Chakraborty, Chen-Huan Chiang

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

Improving path delay testability of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Very Large Scale Integr. Syst., 2000

Path delay fault simulation of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Very Large Scale Integr. Syst., 2000

1999

Built in self test: a complete test solution for telecommunication systems.

Nilanjan Mukherjee, Tapan J. Chakraborty, Ramesh Karri

IEEE Commun. Mag., 1999

1998

A BIST scheme for the detection of path-delay faults.

Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

On variable clock methods for path delay testing of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Effective Path Selection for Delay Fault Testing of Sequential Circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Design for high-speed testability of stuck-at faults.

Tapan J. Chakraborty, Vishwani D. Agrawal

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Simulation of at-speed tests for stuck-at faults.

Tapan J. Chakraborty, Vishwani D. Agrawal

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Robust testing for stuck-at faults.

Tapan J. Chakraborty, Vishwani D. Agrawal

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

High-Performance Circuit Testing with Slow-Speed Testers.

Vishwani D. Agrawal, Tapan J. Chakraborty

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Delay independent initialization of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993

Partial scan testing with single clock control.

Vishwani D. Agrawal, Tapan J. Chakraborty

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Design for Testability for Path Delay faults in Sequential Circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Delay Fault Models and Test Generation for Random Logic Sequential Circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 29th Design Automation Conference, 1992

1991

On behavior fault modeling for digital designs.

Sumit Ghosh, Tapan J. Chakraborty

J. Electron. Test., 1991

Enhanced Controllability for <i>I_DDQ</i> Test Sets Using Partial Scan.

Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin

Proceedings of the 28th Design Automation Conference, 1991

1989

Gentest: An Automatic Test-Generation System for Sequential Circuits.

Wu-Tung Cheng, Tapan J. Chakraborty

Computer, 1989

1988

On Behavior Fault Modeling for Combinational Digital Designs.

Tapan J. Chakraborty, Sumit Ghosh

Proceedings of the Proceedings International Test Conference 1988, 1988