Tao-Tao Zhu

Orcid: 0000-0002-8393-1219

Affiliations:

Zhejiang University, Institute of VLSI Design, Hangzhou, China

According to our database¹, Tao-Tao Zhu authored at least 9 papers between 2015 and 2020.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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Bibliography

2020

A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs.

[BibT_eX]

[DOI]

IEEE Access, 2020

2018

An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Low-power perceptron model based ECG processor for premature ventricular contraction detection.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2018

A low power QRS detection processor with adaptive scaling of processing resolution.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

2017

Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2015

A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Tao-Tao Zhu

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