Tao Lv

Affiliations:

Chinese Academy of Sciences, State Key Laboratory of Computer Architecture, Beijing, China

According to our database¹, Tao Lv authored at least 17 papers between 2003 and 2016.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

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PhD thesis

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Links

On csauthors.net:

Bibliography

2016

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2014

Functional test generation guided by steady-state probabilities of abstract design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Path Constraint Solving Based Test Generation for Hard-to-Reach States.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2010

Fast path selection for testing of small delay defects considering path correlations.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On generation of a universal path candidate set containing testable long paths.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

An abstraction-guided simulation approach using Markov models for microprocessor verification.

[BibT_eX]

[DOI]

Tao Zhang

Tao Lv

Xiaowei Li

Proceedings of the Design, Automation and Test in Europe, 2010

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Graph partition based path selection for testing of small delay defects.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Automatic Selection of Internal Observation Signals for Design Verification.

[BibT_eX]

[DOI]

Tao Lv

Huawei Li

Xiaowei Li

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2007

Bug analysis and corresponding error models in real designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006

Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

2004

Pair Balance-Based Test Scheduling for SOCs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains.

[BibT_eX]

[DOI]

Tao Lv

Jianping Fan

Xiaowei Li

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Tao Lv

Timeline

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