Tao Li

Orcid: 0009-0000-9742-3701

Affiliations:
  • National University of Defense Technology, College of Computer, Changsha, China


According to our database1, Tao Li authored at least 36 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Inference-to-complete: A High-performance and Programmable Data-plane Co-processor for Neural-network-driven Traffic Analysis.
CoRR, 2024

2023
A Deterministic Embedded End-System Tightly Coupled With TSN Schedule.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

TreeSensing: Linearly Compressing Sketches with Flexibility.
Proc. ACM Manag. Data, 2023

Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network.
CoRR, 2023

DRA: Ultra-Low Latency Network I/O for TSN Embedded End-Systems.
Proceedings of the 31st IEEE/ACM International Symposium on Quality of Service, 2023

Poster Abstract: A Network-on-Chip Router Architecture for Industrial Internet-of-Thing Gateways.
Proceedings of the 22nd International Conference on Information Processing in Sensor Networks, 2023

2021
CAMES: enabling centralized automotive embedded systems with time-sensitive network.
Proceedings of the SIGCOMM '21: ACM SIGCOMM 2021 Conference, 2021

MapEmbed: Perfect Hashing with High Load Factor and Fast Update.
Proceedings of the KDD '21: The 27th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2021

2020
MsBV: A Memory Compression Scheme for Bit-Vector-Based Classification Lookup Tables.
IEEE Access, 2020

PPB: a Path-based Packet Batcher to Accelerate Vector Packet Processor.
Proceedings of the 15th International Conference on Computer Science & Education, 2020

Network Programming Interface in General-Purpose Multi-core Processor: A Survey.
Proceedings of the 15th International Conference on Computer Science & Education, 2020

Update Latency Optimization of Packet Classification for SDN Switch on FPGA.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches.
IEICE Trans. Commun., 2019

A Memory Optimized Architecture for Multi-Field Packet Classification (Brief Announcement).
Proceedings of the 31st ACM on Symposium on Parallelism in Algorithms and Architectures, 2019

FAST: enabling fast software/hardware prototype for network experimentation.
Proceedings of the International Symposium on Quality of Service, 2019

A Heterogeneous Parallel Packet Processing Architecture for NFV Acceleration.
Proceedings of the 27th IEEE International Conference on Network Protocols, 2019

STRIDE: Single-Trip-Time Based Reliable Data Transport Protocol for the Reconfigurable Cloud.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

TabTree: A TSS-assisted Bit-selecting Tree Scheme for Packet Classification with Balanced Rule Mapping.
Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018
FAS: Using FPGA to Accelerate and Secure SDN Software Switches.
Secur. Commun. Networks, 2018

Demonstration of Path-Based Packet Batcher for Accelerating Vectorized Packet Processing.
Proceedings of the 15th Annual IEEE International Conference on Sensing, 2018

2016
Design and implementation of Software Defined Hardware Counters for SDN.
Comput. Networks, 2016

Self-described buffer: A novel mechanism to improve packet I/O efficiency in Linux.
Proceedings of the 24th IEEE/ACM International Symposium on Quality of Service, 2016

2015
Towards high-performance packet processing on commodity multi-cores: current issues and future directions.
Sci. China Inf. Sci., 2015

2014
Design of Software Defined hardware counters for SDN.
Proceedings of the 20th IEEE International Workshop on Local & Metropolitan Area Networks, 2014

The Demonstration of Hyper Software Defined Hardware Counters.
Proceedings of the IEEE 6th International Conference on Cloud Computing Technology and Science, 2014

Demostration of Self-Described Buffer for Accelerating Packet Forwarding on Multi-core Servers.
Proceedings of the IEEE 6th International Conference on Cloud Computing Technology and Science, 2014

2013
Towards Internet Innovation: Software Defined Data Plane.
Proceedings of the Frontiers in Internet Technologies, 2013

2012
Neighbor Gradient-based Multicast Routing for Service-Oriented Applications.
KSII Trans. Internet Inf. Syst., 2012

Who is more reliable?: an evaluation method for distributed-memory aggregation in the internet.
Proceedings of the 2012 ACM conference on CoNEXT student workshop, 2012

2011
Accelerating identification of custom instructions for extensible processors.
IET Circuits Devices Syst., 2011

Using NetMagic to observe fine-grained per-flow latency measurements.
Proceedings of the ACM SIGCOMM 2011 Conference on Applications, 2011

Does one size fit all?: the impact of policy on multicast mechanism for future network.
Proceedings of The ACM CoNEXT Student Workshop, 2011

2010
Selecting profitable custom instructions for reconfigurable processors.
J. Syst. Archit., 2010

2009
Fast enumeration of maximal valid subgraphs for custom-instruction identification.
Proceedings of the 2009 International Conference on Compilers, 2009

Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection.
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009

2007
DynaNP - A Coarse-grain Dataflow Network Processor Architecture with Dynamic Configurable Processing Path.
Proceedings of the 8th ACIS International Conference on Software Engineering, 2007


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