Tanusree Kaibartta

According to our database, Tanusree Kaibartta authored at least 7 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs.

Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2021

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC.

Tanusree Kaibartta, G. P. Biswas, Arup Kumar Pal, Debesh Kumar Das

IEEE Access, 2021

2020

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs.

Tanusree Kaibartta, G. P. Biswas, Debesh Kumar Das

J. Electron. Test., 2020

Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing.

Tanusree Kaibartta, G. P. Biswas, Debesh K. Das

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Approach of genetic algorithm for power-aware testing of 3D IC.

Tanusree Kaibartta, Chandan Giri, Hafizur Rahaman, Debesh Kumar Das

IET Comput. Digit. Tech., 2019

2018

Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach.

Tanusree Kaibartta, Debesh Kumar Das

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2015

Testing of 3D IC with minimum power using genetic algorithm.

Tanusree Kaibartta, Debesh K. Das

Proceedings of the 10th International Design & Test Symposium, 2015