Tanay Karnik

Srivatsa Rangachar Srinivasa

Tushar Krishna

Sung Kyu Lim

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Image Processing, 2023

2022

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems.

[BibT_eX]

[DOI]

Jainaveen Sundaram Priya

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Innovations for Intelligent Edge.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021

Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration (Invited).

[BibT_eX]

[DOI]

Akshay Krishna Ramanathan

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation.

[BibT_eX]

[DOI]

Srivatsa Srinivasa

Vijaykrishnan Narayanan

Srivatsa Rangachar Srinivasa

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding.

[BibT_eX]

[DOI]

Jainaveen Sundaram

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Self-Powered IOT System for Edge Inference.

[BibT_eX]

[DOI]

Krishnan Ravichandran

Mukesh Bhartiya

Angela Nicoara

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Mehran Mozaffari Kermani

IEEE Trans. Very Large Scale Integr. Syst., 2019

Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface.

[BibT_eX]

[DOI]

Srinivasan Gopal

Deukhyoun Heo

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes.

[BibT_eX]

[DOI]

Krishnan Ravichandran

James W. Tschanz

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.

[BibT_eX]

[DOI]

Sasikanth Manipatruni

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Technology trends, requirements and challenges for ubiquitous self-powered IOT systems deployment.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

2015

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

2014

Resiliency for many-core system on a chip.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Adaptive and Resilient Circuits for Dynamic Variation Tolerance.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

F5: Frequency generation and clock distribution.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Power management and delivery for high-performance microprocessors.

[BibT_eX]

[DOI]

Mondira (Mandy) Deb Pant

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 22nm dynamically adaptive clock distribution for voltage droop tolerance.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Scaling the "Memory Wall": Designer track.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Design for test and reliability in ultimate CMOS.

[BibT_eX]

[DOI]

Michael Nicolaidis

Lorena Anghel

Nacer-Eddine Zergainoh

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.

[BibT_eX]

[DOI]

Dinesh Somasekhar

IET Comput. Digit. Tech., 2011

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

3DICs for tera-scale computing: a case study.

[BibT_eX]

[DOI]

Dinesh Somasekhar

Proceedings of the 2011 International Symposium on Physical Design, 2011

Integrated inductors with magnetic materials for on-chip power conversion.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

Coordinating 3D designs: Interface IP, standards or free form?

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Resilient microprocessor design for high performance & energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

SRAM dynamic stability estimation using MPFP and its applications.

[BibT_eX]

[DOI]

Microelectron. J., 2009

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Resilient circuits - Enabling energy-efficient performance and reliability.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Circuit techniques for dynamic variation tolerance.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Accurate Estimation of SRAM Dynamic Stability.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Analytical Model for the Propagation Delay of Through Silicon Vias.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters.

[BibT_eX]

[DOI]

Saravanan Rajapandian

IEEE J. Solid State Circuits, 2007

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Low Voltage Buffered Bandgap Reference.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

High-voltage power delivery through charge recycling.

[BibT_eX]

[DOI]

Saravanan Rajapandian

Kenneth L. Shepard

Peter Hazucha

IEEE J. Solid State Circuits, 2006

Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.

[BibT_eX]

[DOI]

Ruchir Puri

Rajiv V. Joshi

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters.

[BibT_eX]

[DOI]

Saravanan Rajapandian

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

High-frequency DC-DC conversion : fact or fiction.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

Area-efficient linear regulator with ultra-fast load regulation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

Design of sub-90nm Circuits and Design Methodologies.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Logic soft errors in sub-65nm technologies design and CAD challenges.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.

[BibT_eX]

[DOI]

Peter Hazucha

Jagdish Patel

IEEE Trans. Dependable Secur. Comput., 2004

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V<sub>T</sub> CMOS process.

[BibT_eX]

[DOI]

Krishnamurthy Soumyanath

IEEE J. Solid State Circuits, 2004

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

HiSIM: hierarchical interconnect-centric circuit simulator.

[BibT_eX]

[DOI]

Tsung-Hao Chen

Jeng-Liang Tsai

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Design and reliability challenges in nanometer technologies.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Parameter variations and impact on circuits and microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Sub-90nm technologies: challenges and opportunities for CAD.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

[BibT_eX]

[DOI]

Venkatesh Govindarajulu

Proceedings of the 39th Design Automation Conference, 2002

1999

Microprocessor Layout Method.

[BibT_eX]

[DOI]

Proceedings of the VLSI Handbook., 1999

1995

An empirical model for accurate estimation of routing delay in FPGAs.

[BibT_eX]

[DOI]

Sung-Mo Kang

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Structural and behavioral synthesis for testability techniques.

[BibT_eX]

[DOI]

Chung-Hsing Chen