Tanausú Ramírez

According to our database1, Tanausú Ramírez authored at least 13 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2020
Revisiting print-attribute optimization: a direct pattern generation approach.
Proceedings of the 28th Color and Imaging Conference, 2020

2013
Capturing vulnerability variations for register files.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
New reliability mechanisms in memory design for sub-22nm technologies.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Hardware/software-based diagnosis of load-store queues using expandable activity logs.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Runahead threads.
PhD thesis, 2010

Efficient runahead threads.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Code Semantic-Aware Runahead Threads.
Proceedings of the ICPP 2009, 2009

2008
Runahead Threads to improve SMT performance.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
Energy saving through a simple load control mechanism.
SIGARCH Comput. Archit. News, 2007

Runahead Threads: Reducing Resource Contention in SMT Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
A simple speculative load control mechanism for energy saving.
Proceedings of the 2006 workshop on MEmory performance, 2006

Kilo-instruction processors, runahead and prefetching.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Kilo-Instruction Processors: Overcoming the Memory Wall.
IEEE Micro, 2005


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