Tamer A. Ali
Affiliations:- MediaTek, Irvine, CA, USA
- Broadcom, Irvine, CA, USA
- University of California, Los Angeles, CA, USA (PhD 2012)
According to our database1,
Tamer A. Ali
authored at least 17 papers
between 2010 and 2024.
Collaborative distances:
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Bibliography
2024
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2021
11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE J. Solid State Circuits, 2013
A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
PhD thesis, 2012
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.
IEEE J. Solid State Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010