Tameesh Suri

According to our database, Tameesh Suri authored at least 11 papers between 2007 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs.

Tameesh Suri, Aneesh Aggarwal

Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2015

System-Level Characterization of Datacenter Applications.

Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan

Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering, Austin, TX, USA, January 31, 2015

Performance analysis of NVMe SSDs and their implication on real world databases.

Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan

Proceedings of the 8th ACM International Systems and Storage Conference, 2015

Performance Characterization of Hyperscale Applicationson on NVMe SSDs.

Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan

Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2015

2014

SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors.

Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri

IEEE Trans. Computers, 2014

2011

SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors.

Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri

Proceedings of the 8th Conference on Computing Frontiers, 2011

2010

Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration.

Tameesh Suri, Aneesh Aggarwal

Int. J. Parallel Program., 2010

2009

Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.

Tameesh Suri, Aneesh Aggarwal

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.

Tameesh Suri, Aneesh Aggarwal

Proceedings of the 6th Conference on Computing Frontiers, 2009

2008

Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware.

Tameesh Suri, Aneesh Aggarwal

Proceedings of the High Performance Computing, 2008

2007

Improving instruction level parallelism through reconfigurable units in superscalar processors.

Tameesh Suri

SIGARCH Comput. Archit. News, 2007