Takuya Wadatsumi

Orcid: 0000-0003-3062-9523

According to our database1, Takuya Wadatsumi authored at least 7 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2022
2023
2024
0
1
2
3
4
5
1
4
1
1

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Links

On csauthors.net:

Bibliography

2024
Si-Backside Side-Channel Leakage Measurement and Simulation.
Proceedings of the 21st International SoC Design Conference, 2024

Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips.
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2024

Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection.
Proceedings of the 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2024

On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

2023
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging.
IEICE Trans. Electron., October, 2023

Characterization of Backside ESD Impacts on Integrated Circuits.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging.
Proceedings of the IEEE International Reliability Physics Symposium, 2022


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