Takuya Sawada
According to our database1,
Takuya Sawada
authored at least 11 papers
between 2011 and 2023.
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Bibliography
2023
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging.
IEICE Trans. Electron., October, 2023
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2019
Proceedings of the 7th ACIS International Conference on Applied Computing and Information Technology, 2019
2015
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
An insertion loss control method for supplementing cancellation effect deteriorated by echo path change in hands free telecommunication system.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2012
IEICE Trans. Electron., 2012
2011