Takushi Hashida

According to our database, Takushi Hashida authored at least 11 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Managing Non-Volatile Memory in Database Systems.

Alexander van Renen, Viktor Leis, Alfons Kemper, Thomas Neumann, Takushi Hashida, Kazuichi Oe, Yoshiyasu Doi, Lilian Harada, Mitsuru Sato

Proceedings of the 2018 International Conference on Management of Data, 2018

2015

Design of a Shared Memory mechanism for efficient paralell processing in PostgreSQL.

Yoshifumi Ujibashi, Minoru Nakamura, Tsuguchika Tabaru, Takushi Hashida, Motoyuki Kawaba, Lilian Harada

Proceedings of the 6th International Conference on Information, 2015

2014

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

IEEE J. Solid State Circuits, 2013

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration.

Takushi Hashida, Makoto Nagata

IEEE J. Solid State Circuits, 2011

A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength.

Takushi Hashida, Yuuki Araga, Makoto Nagata

IEICE Trans. Electron., 2011

A diagnosis testbench of analog IP cores against on-chip environmental disturbances.

Takushi Hashida, Yuuki Araga, Makoto Nagata

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails.

Takushi Hashida, Makoto Nagata

IEICE Trans. Electron., 2010

An on-chip waveform capturing technique pursuing minimum cost of integration.

Yuuki Araga, Takushi Hashida, Makoto Nagata

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2007

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration.

Koichiro Noguchi, Takushi Hashida, Makoto Nagata

IEICE Trans. Electron., 2007