Takuro Amashita

According to our database, Takuro Amashita authored at least 4 papers between 2011 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process.

Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.

Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2012

Neutron-induced soft error rate estimation for SRAM using PHITS.

Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.

Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011