Takumi Uezono

According to our database, Takumi Uezono authored at least 27 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Vulnerability Estimation of DNN Model Parameters with Few Fault Injections.

Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

An Intelligent Diagnostic Technique for Reliable Operation of Edge AI.

Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Subrata Kumar Kundu

Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023

2022

Achieving Automotive Safety Requirements through Functional In-Field Self-Test for Deep Learning Accelerators.

Takumi Uezono, Yi He, Yanjing Li

Proceedings of the IEEE International Test Conference, 2022

Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections.

Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Efficient Functional In-Field Self-Test for Deep Learning Accelerators.

Yi He, Takumi Uezono, Yanjing Li

Proceedings of the IEEE International Test Conference, 2021

2020

Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing.

Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto

Proceedings of the IEEE International Test Conference, 2020

2016

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.

Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato

J. Electron. Test., 2016

Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation.

Takumi Uezono, Tadanobu Toba, Ken-ichi Shimbo, Fumihiko Nagasaki, Kenji Kawamura

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014

A Variability-Aware Adaptive Test Flow for Test Quality Improvement.

Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2010

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation.

Takumi Uezono, Kazuya Masu, Takashi Sato

IEICE Trans. Electron., 2010

Path clustering for adaptive test.

Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Scan based process parameter estimation through path-delay inequalities.

Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Decomposition of drain-current variation into gain-factor and threshold voltage variations.

Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

One-Shot Voltage-Measurement Circuit Utilizing Process Variation.

Takumi Uezono, Takashi Sato, Kazuya Masu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information.

Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network.

Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Adaptable wire-length distribution with tunable occupation probability.

Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Weakness Identification for Effective Repair of Power Distribution Network.

Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.

Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Improvement of power distribution network using correlation-based regression analysis.

Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Statistical Modeling of a Via Distribution for Yield Estimation.

Takumi Uezono, Kenichi Okada, Kazuya Masu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.

Kenichi Okada, Takumi Uezono, Kazuya Masu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Via Distribution Model for Yield Estimation.

Takumi Uezono, Kenichi Okada, Kazuya Masu

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

Wire Length Distribution Model for System LSI.

Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Prediction of delay time for future LSI using on-chip transmission line interconnects.

Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu

Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Wire Length Distribution Model Considering Core Utilization for System on Chip.

Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Evaluation of on-chip transmission line interconnect using wire length distribution.

Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005