Taku Toshikawa
According to our database1,
Taku Toshikawa
authored at least 5 papers
between 2012 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
2012
2013
2014
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2018
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2018
An ultra-wide range (0.01-240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator.
IEICE Electron. Express, 2018
2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs.
IEICE Electron. Express, 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2012
IEICE Trans. Electron., 2012