Takio Ohno

According to our database1, Takio Ohno authored at least 6 papers between 1988 and 1990.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

1988
1989
1990
0
1
2
3
4
1
3
2

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1990
A 100-mega-access per second matching memory for a data-driven microprocessor.
IEEE J. Solid State Circuits, February, 1990

1989
A 400 K-transistor CMOS sea-of-gates array with continuous track allocation.
IEEE J. Solid State Circuits, October, 1989

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme.
IEEE J. Solid State Circuits, October, 1989

VLSI implementation of a variable-length pipeline scheme for data-driven processors.
IEEE J. Solid State Circuits, August, 1989

1988
An elastic pipeline mechanism by self-timed circuits.
IEEE J. Solid State Circuits, February, 1988

A macrocell approach for VLSI processor design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988


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