Takio Ohno

According to our database, Takio Ohno authored at least 5 papers between 1988 and 1989.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1989

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation.

Masatomi Okabe, Yoshihiro Okuno, Takahiko Arakawa, Ichiro Tomioka, Takio Ohno, Tomoyoshi Noda, Masahiro Hatanaka, Yoichi Kuramitsu

IEEE J. Solid State Circuits, October, 1989

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme.

Shinji Komori, Hidehiro Takata, Todhixuki Tamura, Fumixsdu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Hiroaki Nishikawa, Hiroaki Terada

IEEE J. Solid State Circuits, October, 1989

VLSI implementation of a variable-length pipeline scheme for data-driven processors.

Tetsuo Yamasaki, Kenji Shima, Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Hiroaki Terada

IEEE J. Solid State Circuits, August, 1989

1988

An elastic pipeline mechanism by self-timed circuits.

Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Katsuhiko Asada, Hiroaki Terada

IEEE J. Solid State Circuits, February, 1988

A macrocell approach for VLSI processor design.

Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988