Takeshi Yoshimura

Tatsuhiro Chiba

Hiroshi Horii

Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

Towards Selecting Best Combination of SQL-on-Hadoop Systems and JVMs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2017

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2017

A Unified Scheduling Approach for Power and Resource Optimization With Multiple Vdd or/and Vth in High-Level Synthesis.

[BibT_eX]

[DOI]

Nan Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Real-Time UHD Background Modelling with Mixed Selection Block Updates.

[BibT_eX]

[DOI]

Axel Beaugendre

Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

3D-IC signal TSV assignment for thermal and wirelength optimization.

[BibT_eX]

[DOI]

Yuxin Qian

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A particle swarm optimization and branch and bound based algorithm for economical smart home scheduling.

[BibT_eX]

[DOI]

Yangyizhou Wang

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Approximate-DCT-derived measurement matrices for compressed sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Measurement-domain intra prediction framework for compressively sensed images.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Energy-efficient scheduling method with cross-loop model for resource-limited CNN accelerator designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Application of on-line machine learning in optimization algorithms: A case study for local search.

[BibT_eX]

[DOI]

Proceedings of the 2017 9th Computer Science and Electronic Engineering Conference, 2017

A force directed partitioning algorithm for 3D floorplanning.

[BibT_eX]

[DOI]

Linquan Lyu

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Case for Static Analysis of Linux to Find Faults in Interrupt Request Handlers.

[BibT_eX]

[DOI]

J. Inf. Process., 2016

An efficient algorithm for 3D-IC TSV assignment.

[BibT_eX]

[DOI]

Nan Ding

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Thermal-aware floorplanning for NoC-sprinting.

[BibT_eX]

[DOI]

Hui Zhu

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Economical smart home scheduling for single and multiple users.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

2015

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Tabu search based multiple voltage scheduling under both timing and resource constraints.

[BibT_eX]

[DOI]

Jianmo Ni

Nan Wang

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Primal-dual method based simultaneous functional unit and register binding.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Leakage Power Aware Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

FoxyFeed: Forging Device-Level Asynchronous Events for Kernel Development.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014

Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder.

[BibT_eX]

[DOI]

Proceedings of the Advances in Multimedia Information Processing - PCM 2014, 2014

Do Injected Faults Cause Real Failures? A Case Study of Linux.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Software Reliability Engineering Workshops, 2014

Who Writes What Checkers? - Learning from Bug Repositories.

[BibT_eX]

[DOI]

Proceedings of the 10th Workshop on Hot Topics in System Dependability, 2014

Integration of Push-Based and Pull-Based Connectivity Status Sharing for Efficient Data Forwarding towards Mobile Sinks in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Advanced Information Networking and Applications, 2014

2013

Using Fault Injection to Analyze the Scope of Error Propagation in Linux.

[BibT_eX]

[DOI]

Hiroshi Yamada

Inf. Media Technol., 2013

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Nan Liu

IEICE Trans. Electron., 2013

Min-cut based leakage power aware scheduling in high-level synthesis.

[BibT_eX]

[DOI]

Nan Wang

Proceedings of the International Symposium on Quality Electronic Design, 2013

Mobility overlap-removal based leakage power aware scheduling in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Power and resource aware scheduling with multiple voltages.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Timing and resource constrained leakage power aware scheduling in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Interconnection allocation between functional units and registers in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Genetic Algorithm based pipeline scheduling in high-level synthesis.

[BibT_eX]

[DOI]

Xiaohao Gao

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

Floorplanning for High Utilization of Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Nan Liu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Port assignment for interconnect reduction in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Application-Specific Network-on-Chip synthesis with topology-aware floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Practically scalable floorplanning with voltage island generation.

[BibT_eX]

[DOI]

Xiaolin Zhang

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Is Linux Kernel Oops Useful or Not?

[BibT_eX]

[DOI]

Hiroshi Yamada

Proceedings of the Eighth Workshop on Hot Topics in System Dependability, HotDep 2012, 2012

Wirelength driven I/O buffer placement for flip-chip with timing-constrained.

[BibT_eX]

[DOI]

Nan Liu

Shiyu Liu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Can Linux be Rejuvenated without Reboots?

[BibT_eX]

[DOI]

Hiroshi Yamada

Proceedings of the IEEE Third International Workshop on Software Aging and Rejuvenation, 2011

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Floorplanning driven Network-on-Chip synthesis for 3-D SoCs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Hypothesis Preservation Approach to Scene Text Recognition with Weighted Finite-State Transducer.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Document Analysis and Recognition, 2011

A low power technology mapping method for Adaptive Logic Module.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

An effecient level-shifter floorplanning method for Multi-voltage design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Mobility overlap-removal based timing-constrained scheduling.

[BibT_eX]

[DOI]

Yuan Yao

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints.

[BibT_eX]

[DOI]

Integr., 2010

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Whitespace insertion for through-silicon via planning on 3-D SoCs.

[BibT_eX]

[DOI]

Wei Zhong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Post-scheduling frequency assignment for energy-efficient high-level synthesis.

[BibT_eX]

[DOI]

Ru Liu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Acoustic OFDM system and its extension.

[BibT_eX]

[DOI]

Yusuke Nakashima

Vis. Comput., 2009

Exploration of Schedule Space by Random Walk.

[BibT_eX]

[DOI]

Liangwei Ge

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Performance enhancement of TFI-OFDM with path selection based channel identification.

[BibT_eX]

[DOI]

Digit. Signal Process., 2009

Lagrangian relaxation based register placement for high-performance circuits.

[BibT_eX]

[DOI]

Mei-Fang Chiang

Takumi Okamoto

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A generalized V-shaped multilevel method for large scale floorplanning.

[BibT_eX]

[DOI]

Zheng Xu

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

[BibT_eX]

[DOI]

Mei-Fang Chiang

Takumi Okamoto

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Data Transmission on AM Broadcast with Acoustic OFDM.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2008

Acoustic OFDM System and Performance Analysis.

[BibT_eX]

[DOI]

Yusuke Nakashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Acoustic OFDM: Embedding High Bit-Rate Data in Audio.

[BibT_eX]

[DOI]

Proceedings of the Advances in Multimedia Modeling, 2008

2007

Score Sequence Pair Problems of (r11, r12, r22)-Tournaments - - Determination of Realizability - - .

[BibT_eX]

[DOI]

Masaya Takahashi

Takahiro Watanabe

IEICE Trans. Inf. Syst., 2007

Max-Flow Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

Liangwei Ge

Kazutoshi Wakabayashi

Takashi Takenaka

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A stable fixed-outline floorplanning method.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair.

[BibT_eX]

[DOI]

Masaya Takahashi

Takahiro Watanabe

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Domino Logic Synthesis System and its Applications.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2006

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament.

[BibT_eX]

[DOI]

Masaya Takahashi

Takahiro Watanabe

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Wireless video applications in 3G and beyond.

[BibT_eX]

[DOI]

Minoru Etoh

IEEE Wirel. Commun., 2005

Real-time video transport optimization using streaming agent over 3G wireless networks.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2005

Advances in Wireless Video Delivery.

[BibT_eX]

[DOI]

Minoru Etoh

Proc. IEEE, 2005

An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs.

[BibT_eX]

[DOI]

Ko Yoshikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Double feedback streaming agent for real-time delivery of media over 3G wireless networks.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2004

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Timing optimization by replacing flip-flops to latches.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A Robust Method for Soft IP Handover.

[BibT_eX]

[DOI]

Tomoyuki Ohya

IEEE Internet Comput., 2003

A System Architecture for Managing Mobile Streaming Media Service.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Distributed Computing Systems Workshops (ICDCS 2003 Workshops), 2003

End-to-end robust IP soft handover.

[BibT_eX]

[DOI]

Tomoyuki Ohya

Proceedings of IEEE International Conference on Communications, 2003

2002

Multiple-Reference Compression of RTP/UDP/IP Headers for Mobile Multimedia Communications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A Minimum Bandwidth Guaranteed Service Model and Its Implementation on Wireless Packet Scheduler.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Mobile streaming media CDN enabled by dynamic SMIL.

[BibT_eX]

[DOI]

Proceedings of the Eleventh International World Wide Web Conference, 2002

Rate-distortion optimized application-level retransmission using streaming agent for video streaming over 3G wireless network.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Conference on Image Processing, 2002

Rate and robustness control with RTP monitoring agent for mobile multimedia streaming.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2002

Streaming agent for wired network/wireless link rate-mismatch environment.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th Workshop on Multimedia Signal Processing, 2002

2001

RObust Header Compression (ROHC): Framework and four profiles: RTP, UDP, ESP, and uncompressed.

[BibT_eX]

[DOI]

RFC, July, 2001

Floorplanning using a tree representation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000

An enhanced perturbing algorithm for floorplan design using the O-tree representation.

[BibT_eX]

[DOI]

Yingxin Pang

Chung-Kuan Cheng

Proceedings of the 2000 International Symposium on Physical Design, 2000

1999

An O-Tree Representation of Non-Slicing Floorplan and Its Applications.

[BibT_eX]

[DOI]

Pei-Ning Guo

Chung-Kuan Cheng

Proceedings of the 36th Conference on Design Automation, 1999

1995

A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1992

A Multi-Layer Channel Router with New Style of Over-the-Cell Routing.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1990

New Placement and Global Routing Algorithms for Standard Cell Layouts.

[BibT_eX]

[DOI]

Masato Edahiro

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

A rule-based and algorithmic approach for logic synthesis.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 1989

A resource sharing and control synthesis method for conditional branches.

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A single chip VLSI chrominance/luminance separator based on a silicon compiler.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1989

1987

Compaction-Based Custom LSI Layout Design Method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1984

An efficient channel router.

[BibT_eX]

[DOI]

Proceedings of the 21st Design Automation Conference, 1984

1982

Efficient Algorithms for Channel Routing.

[BibT_eX]

[DOI]