Takeshi Tokuda

According to our database, Takeshi Tokuda authored at least 7 papers between 1983 and 1993.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1993

Fuzzy inference and fuzzy inference processor.

Kazuo Nakamura, Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Takeshi Tokuda

IEEE Micro, 1993

A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.

Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1991

A Data-Driven Architecture for Distributed Parallel Processing.

Toshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

Built-in self-test in a 24 bit floating point digital signal processor.

Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

A macrocell approach for VLSI processor design.

Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1984

A Hierarchical Standard Cell Approach for Custom VLSI Design.

Takeshi Tokuda, Jiro Korematsu, Osamu Tomisawa, Sotoju Asai, Isao Ohkura, Tatsuya Enomoto

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1983

Delay-Time Modeling for ED MOS Logic LSI.

Takeshi Tokuda, Kaoru Okazaki, Kazuhiro Sakashita, Isao Ohkura, Tatsuya Enomoto

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983