Takeshi Shiro
According to our database1,
Takeshi Shiro
authored at least 2 papers
between 2007 and 2013.
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Bibliography
2013
Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2007
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007