Takeshi Ohkawa

Masahiro Aoyagi

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023

2022

IoT Edge Server ROS Node Allocation Method for Multi-SLAM on Many-core.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2022

FPGA-Based Control of Remote Robotic Hands and ROS2 Integration.

[BibT_eX]

[DOI]

Ludi Wang

Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

Desgin and Implementation of ROS2-based Autonomous Tiny Robot Car with Integration of Multiple ROS2 FPGA Nodes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

Fogcached-Ros: DRAM/NVMM Hybrid KVS Server with ROS Based Extension for ROS Application and SLAM Evaluation.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2021

Layer Modeling and Its Code Generation based on Context-oriented Programming.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Model-Driven Engineering and Software Development, 2021

A dataset generation for object recognition and a tool for generating ROS2 FPGA node.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

Power Consumption Reduction Method and Edge Offload Server for Multiple Robots.

[BibT_eX]

[DOI]

Proceedings of the Edge Computing - EDGE 2021, 2021

2020

Genetic Node-Mapping Methods for Rapid Collective Communications.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2020

Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

FPGA Acceleration of ROS2-Based Reinforcement Learning Agents.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019

Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

Automatic Generation Tool of FPGA Components for Robots.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

Directive-Based Parallelization of For-Loops at LLVM IR Level.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/ACIS International Conference on Software Engineering, 2019

Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

High level synthesis of ROS protocol interpretation and communication circuit for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Robotics Software Engineering, 2019

Design and Development of Networked Multiple FPGA Components for Autonomous Tiny Robot Car.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster.

[BibT_eX]

[DOI]

Proceedings of the Advanced Information Networking and Applications, 2019

2018

A Genetic Approach for Accelerating Communication Performance by Node Mapping.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2018

FPGA Components for Integrating FPGAs into Robot Systems.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2018

Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster.

[BibT_eX]

[DOI]

Proceedings of the 11th Workshop on General Purpose Processing using GPUs, 2018

Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster.

[BibT_eX]

[DOI]

Proceedings of the 2018 Workshop on Advanced Tools, 2018

An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

2017

Performance of Android Cluster System Allowing Dynamic Node Reconfiguration.

[BibT_eX]

[DOI]

Wirel. Pers. Commun., 2017

A Static Packet Scheduling Approach for Fast Collective Communication by Using PSO.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Translation Method of ARM Machine Code to LLVM-IR for Binary Code Parallelization and Optimization.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

2016

Enhancing Entropy Throttling: New Classes of Injection Control in Interconnection Networks.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

Architecture exploration of intelligent robot system using ros-compliant FPGA component.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

cReComp: Automated Design Tool for ROS-Compliant FPGA Component.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Introducing PSO for Optimal Packet Scheduling of Collective Communication.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

Relaxing Heavy Congestion by State Propagation.

[BibT_eX]

[DOI]

J. Inf. Process., 2015

Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems.

[BibT_eX]

[DOI]

CoRR, 2015

Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

An Android cluster system capable of dynamic node reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015

Entropy Throttling: Towards Global Congestion Control of Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Computing and Networking, 2015

Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Computing and Networking, 2015

Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Computing and Networking, 2015

Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Computing and Networking, 2015

2013

Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2013

A Cellular Automata Approach for Large-Scale Interconnection Network Simulation.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

Efficient Data Communication Using Dynamic Switching of Compression Method.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation.

[BibT_eX]

[DOI]