Takeshi Nakayama
According to our database1,
Takeshi Nakayama
authored at least 19 papers
between 1988 and 2022.
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Bibliography
2022
Frequency Error Compensation of Unsynchronized Bistatic CW- MIMO Radar for Multiple Human-Body Localization.
IEEE Trans. Biomed. Circuits Syst., 2022
2021
Estimation Method of the Number of Targets Using Cooperative Multi-Static MIMO Radar.
IEICE Trans. Commun., 2021
2019
Human Activity Identification by Height and Doppler RCS Information Detected by MIMO Radar.
IEICE Trans. Commun., 2019
Proceedings of the Short Paper Proceedings of the Tenth International Conference on Indoor Positioning and Indoor Navigation - Work-in-Progress Papers (IPIN-WiP 2019) co-located with the Tenth International Conference on Indoor Positioning and Indoor Navigation (IPIN 2019), Pisa, Italy, September 30th, 2019
2018
RSSI-Based Living-Body Radar Using Single RF Front-End and Tunable Parasitic Antennas.
IEICE Trans. Commun., 2018
2016
Evaluation of fast human localization and tracking using MIMO radar in multi-path environment.
Proceedings of the 27th IEEE Annual International Symposium on Personal, 2016
2001
IEEE J. Solid State Circuits, 2001
1999
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.
IEEE J. Solid State Circuits, 1999
1998
Proceedings of the Fourteenth International Conference on Pattern Recognition, 1998
1997
Application of neuro-based optimization algorithm to three dimensional cylindric puzzles.
Proceedings of International Conference on Neural Networks (ICNN'97), 1997
Recognition of Essential Folding Operations: A Step for Interpreting Illustrated Books of Origami.
Proceedings of the 4th International Conference Document Analysis and Recognition (ICDAR '97), 1997
1996
Proceedings of the 13th International Conference on Pattern Recognition, 1996
Proceedings of International Conference on Neural Networks (ICNN'96), 1996
1995
Neural network approach to traveling salesman problem based on hierarchical city adjacency.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
1994
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.
IEEE J. Solid State Circuits, April, 1994
1992
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories.
IEEE J. Solid State Circuits, April, 1992
1989
IEEE J. Solid State Circuits, October, 1989
IEEE J. Solid State Circuits, August, 1989
1988
IEEE J. Solid State Circuits, February, 1988