Takeshi Kumaki

According to our database1, Takeshi Kumaki authored at least 36 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Verification of Animal External Ear Model-based Microphone Sensor for Hazardous Sound Detection.
Proceedings of the 6th International Symposium on Advanced Technologies and Applications in the Internet of Things, 2024

2022
Development and evaluation of the "Stego-panel IV" Invisible information lighting display.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Implementation of AI characteristic motion detecting for improper-photography prevention system.
Proceedings of the 19th International SoC Design Conference, 2022

2021
A Study on Specific Emitter Identification Using Modified Allan Variance and Correlation Coefficient.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Development of invisible information lighting display "Stego-panel IV".
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Implementation and Evaluation of Block Cipher Algorithm with Content Addressable Memory-Based Massive-Parallel SIMD Matrix Core.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2020
Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Live Demonstration: Development of LED-Based Stego-Panel for New Smartphone Usage.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Distributed Embedding Approach for Max-Plus Algebra-Based Morphological Wavelet Transform Watermarking.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

2017
Hierarchical-Masked Image Filtering for Privacy-Protection.
IEICE Trans. Inf. Syst., 2017

2015
Proposal of LED-based Peeping Prevention System.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Design and LSI prototyping of security module with hardware trojan.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Development of LED illumination-based spy photo-prevention system.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Detection technique for hardware Trojans using machine learning in frequency domain.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014
Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices.
IEICE Trans. Inf. Syst., 2014

Cellular automaton based pixel-level snakes.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Evaluation of advanced pixel-level snakes on cellular hardware platform.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Development of effective information-hiding method for embedded systems.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Cipher-destroying and secret-key-emitting hardware Trojan against AES core.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Hierarchical image-scrambling method with scramble-level controllability for privacy protection.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Hardware Trojan for security LSI.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

A CAM-Based Separated BTB for a Superscalar Processor.
Proceedings of the First International Symposium on Computing and Networking, 2013

2011
A Scalable Massively Parallel Processor for Real-Time Image Processing.
IEEE J. Solid State Circuits, 2011

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems.
IEICE Trans. Inf. Syst., 2011

2010
A scalable massively parallel processor for real-time image processing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Trans. Electron., 2008

2007
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Trans. Inf. Syst., 2007

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.
IEICE Trans. Inf. Syst., 2007

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Trans. Inf. Syst., 2007

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A flexible multiport content-addressable memory.
Syst. Comput. Jpn., 2006

Application of Multi-ported CAM for Parallel Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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