Takeo Yamashita
According to our database1,
Takeo Yamashita
authored at least 5 papers
between 1993 and 2016.
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Bibliography
2016
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2001
Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
1995
Proceedings of the Advances in Neural Information Processing Systems 8, 1995
1993
Proceedings of the Advances in Neural Information Processing Systems 6, 1993